1. Field of the Invention
The present invention relates generally to the field of integrated circuit manufacturing technology and, more particularly, to a method for depositing selected target atoms.
2. Background of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In the manufacturing of integrated circuits, numerous microelectronic circuits are simultaneously manufactured on semiconductor substrates. These substrates are usually referred to as wafers. A typical wafer is comprised of a number of different regions, known as die regions. When fabrication is complete, the wafer is cut along these die regions to form individual die. Each die contains at least one microelectronic circuit, which is typically packaged and combined with other circuits to form a desired electronic device, such as a computer. Examples of microelectronic circuits which can be fabricated in this way include a microprocessor and a memory, such as a dynamic random access memory (“DRAM”).
Although referred to as semiconductor devices, integrated circuits are in fact fabricated from numerous materials of varying electrical properties. These materials include insulators or dielectrics, such as silicon dioxide, and conductors, such as aluminum or tungsten, in addition to semiconductors, such as silicon and germanium. These various materials are fabricated and arranged on the wafer to form electrical circuits.
For instance, in the manufacture of integrated circuits, conductive paths are formed to connect different circuit elements that have been fabricated within a die. Such connections are typically formed within structures, such as trenches or holes. For example, conductive lines may be fabricated by depositing conductive material within trenches, and contacts or interconnections may be fabricated by depositing conductive material within openings in intermediate insulative layers. These openings are typically referred to as “contact openings” or “vias.” A contact opening is usually created to expose an active region, commonly referred to as a doped region, while vias traditionally refer to any conductive path between any two or more layers in a semiconductor device.
After a contact opening, for instance, has been formed to expose an active region of the semiconductor substrate, an enhanced doping may be performed through the opening to create a localized region of increased carrier density within the bulk substrate. This enhanced region provides a better electrical connection with the conductive material which is subsequently deposited within the opening. One method of increasing conductivity further involves the deposition of a thin titanium-containing film, such as titanium silicide, over the wafer so that it covers the enhanced region at the bottom of the contact opening prior to deposition of the conductive layer. Once the bottom of the contact opening has been lined with a thin titanium-containing film, it is usually desirable to fill the contact opening with a conductive material, such as titanium, to complete the formation of the contact.
Of course, it should also be noted that thin films of titanium-containing compounds find other uses as well in the fabrication of integrated circuits. For example, titanium nitride is used as a diffusion barrier to prevent chemical attack of the substrate, as well as to provide a good adhesive surface for the subsequent deposition of tungsten. Indeed, many reasons exist for depositing thin films between adjacent layers in a semiconductor device. For example, thin films may be used to prevent interdiffusion between adjacent layers or to increase adhesion between adjacent layers. Titanium nitride, titanium silicide, and metallic titanium are known in the art as materials that can be deposited as thin films to facilitate adhesion and to reduce interdiffusion between the layers of a semiconductor device. Other films that may be useful for these purposes also include titanium tungsten, tantalum nitride, and the ternary alloy composed of titanium, aluminum, and nitrogen.
The deposition of titanium and titanium-containing material is just one example of a step in the manufacture of semiconductor wafers. Indeed, any number of thin films, insulators, semiconductors, and conductors may be deposited onto a wafer to fabricate an integrated circuit. As the size of the microelectronic circuits, and therefore the size of die regions, decreases, the percentage of reliable circuits produced on any one wafer becomes highly dependent on the ability to deposit these thin films uniformly at the bottom of the trenches and contact openings and to fill the trenches and contact openings with conductive material.
Integrated circuit technology has advanced through continuing improvements in photolithographic processing so that smaller and smaller features can be patterned onto the surface of a substrate. These smaller features not only make the resulting electronic circuits more compact, but they also make the circuits operate at a higher speed. However, as contact structures, such as trenches, contact openings, and vias, are made smaller, they become more difficult to fill.
To begin to appreciate this problem, it should be understood that the lateral dimension of such structures is typically referred to as the “width” and the vertical dimension of such structures is typically referred to as the “depth.” The aspect ratio is the ratio of depth to width. Thus, as the features have become smaller, the aspect ratio has risen, resulting in high aspect structures. As discussed above, these high aspect ratio structures usually must be filled with an appropriate material before continued processing. Most often the objective is to provide void-free, and preferably seam-free, filling of such structures. Indeed, many different techniques have been developed in an effort to address this problem. For example, films may be deposited by several different methods, such as spin-on deposition, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and physical deposition.
In spin-on deposition, the material to be deposited is mixed with a suitable solvent and spun onto the substrate. The primary disadvantage of spin-on deposition is that nominal uniformity can only be achieved at relatively high thicknesses. Furthermore, this technique often covers high aspect ratio structures without filling them, thus resulting in voids. Therefore, this method is primarily used for the deposition of photoresist and the like, and it is generally not useful for the deposition of thin films or the filling of high aspect ratio structures.
Of the methods mentioned above, it is arguable that CVD and PECVD are best suited to deposit the thinnest films. However, films deposited in this manner tend to exhibit relatively conformal deposition on slanted or vertical surfaces as well as on the bottom surfaces of the trenches and contact openings. While such conformal deposition of thin films certainly finds many uses in the fabrication of integrated circuits, it tends to be somewhat problematic when the goal of a particular process step is to deposit a thin film only at the bottom of a structure or to fill a high aspect ratio structure. Because most deposition techniques of this type inherently deposit material on the sidewalls at the same rate as at the bottom of a contact structure, the sidewall deposition tends to close off the opening of the structure before the structure is completely filled. When the structure is closed off in this manner, a void exists within the structure and a seam exists at the opening. Voids are undesirable in a contact structure because air does not conduct electricity well, and seams are undesirable because solvents and the like which tend to accumulate in the seams can degrade the contact. Thus, chemical vapor deposition techniques are generally only successfully used for moderate aspect ratio structures where sidewall deposition does not close off the structure before it is filled.
In sputter deposition, the material to be deposited, typically referred to as the target, is bombarded with positive inert ions. Once the material exceeds its heat of sublimation, target atoms are ejected into the gas phase where they are subsequently deposited onto the substrate. Sputter deposition has been widely used in integrated circuit processes to deposit titanium-containing films. However, the primary disadvantage of sputter deposition is that high aspect ratio structures are difficult to fill due to “shadowing” effects. Shadowing effects are produced due to the fact that the sputtered particles tend to travel in random or uncontrolled directions, i.e., isotropically, and thus strike the sidewalls of the contact structure at an angle. The particles therefore are deposited on the sidewalls, causing a film growth on the sidewalls. The sidewall film growth eventually closes off the via before it is filled. This problem is often acute in the case of multi-layer metal (MLM) designs where high aspect ratio vias are etched into a dielectric layer and metal must be deposited to fill the via.
To fill a contact structure, it is desirable to deposit films that form preferentially at the bottom of the structure rather than on the sidewalls. Thus, physical deposition techniques, such as sputtering, which produce isotropically traveling particles were traditionally limited for use in filling low aspect ratio structures. However, various techniques for directing sputtered target atoms toward the wafer have been developed in efforts to address the problem of isotropically traveling particles collecting on the sidewalls of the contact structure. For example, collimators have been employed to prevent randomly directed atoms from reaching the surface of the wafer. In collimated sputtering, lattice-shaped collimators block particles traveling towards the wafer at unacceptable angles. Such collimators typically have high aspect ratio tunnels that allow only particles having acceptable trajectories to pass through. The remaining particles impact and deposit on the sidewalls of the collimator, rather than on the sidewalls of the contact structures on the wafer. However, since fewer than 50% of the sputtered particles tend to travel in the shadow angle of 90°+/−5°, most of the particles deposit onto the collimator rather than on the wafer. Thus, while collimators prevent much of the undesirable build up of particles on the sidewalls of contact structures, they do so at the expense of low deposition rates and a high degree of particulate contamination from the material deposited on the collimator sidewalls. Moreover, collimators provide limited directionality, as the particles leaving the collimator still. typically have ±5° variation in their trajectories.
In an effort to improve the deposition rate of collimated sputtering, the wafers have been electrically charged to attract charged titanium ions, and complex induction coils have been used to create a magnetic field to enhance the life time of titanium ions. Because these techniques cause the titanium ions to travel in a direction substantially perpendicular to the wafer, they increase the number of sputtered particles that will pass through the collimator for deposition on the wafer. However, these techniques affect all particles in a similar manner. In other words, the charged wafer attracts all ions, not just titanium ions, and the magnetic field enhances the life time of all ions, not just titanium ions. Thus, these techniques will ionize argon particles as well, which bombard and damage the wafer.
The present invention may address one or more of the problems set forth above.